C5001 Datasheet - International

C5001 Low Skew Muliple Frequency PCI Clock Generator with EMI Reducing SSCG

Pin Number 2 Pin Name XIN PWR VDDA I/O I Description This pin is the connection point for the devices Loop reference frequency. This may be either a CMOS 3.3 volt reference clock or the output of an external crystal. A nominal 14.31818 MHz frequency must be supplied to obtain the frequencies listed .

C5001 Features

* S S S S S S S S S S S S Produces PCI output clocks that are individually 2 selectable for 33.3 or 66.6 MHz under I C or strapping control. Separate output buffer power supply for reduced noise, crosstalk and jitter. input clock frequency standard 14.31818 MHz Output clocks frequency individually se

C5001_International.pdf