C5001 - Low Skew Muliple Frequency PCI Clock Generator with EMI Reducing SSCG

Product Overview

International

Part number	C5001
Manufacturer	International
File Size	138.21 KB
Description	Low Skew Muliple Frequency PCI Clock Generator with EMI Reducing SSCG
Datasheet	C5001 Datasheet
Additional preview pages of the C5001 datasheet.

Pin Number 2 Pin Name XIN PWR VDDA I/O I Description This pin is the connection point for the devices Loop reference frequency.

S S S S S S S S S S S S Produces PCI output clocks that are individually 2 selectable for 33.3 or 66.6 MHz under I C or strapping control. Separate output buffer power supply for reduced noise, crosstalk and jitter. input clock frequency standard 14.31818 MHz Output clocks frequency individually selectable via 2 I C or hardware bi-directional pin strapping. SSCG EMI reduction at 1.0% width 2 Individual clock disables via I C control All output clocks skewed within a 500 pS window Cycle to Cycle.

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Published: Apr 22, 2005 |