C5002 Datasheet - International

C5002 Low Skew Muliple Frequency PCI Clock Generator with EMI Reducing SSCG

Pin Number 2 Pin Name XIN PWR VDDA I/O I Description This pin is the connection point for the devices Loop reference frequency. This may be either a CMOS 3.3 volt reference clock or the output of an external crystal. A nominal 14.31818 MHz frequency must be supplied to obtain the frequencies listed .

C5002 Features

* Produces PCI output clocks that are individually selectable for 33.3 or 66.6 MHz under SMBus or strapping control. Separate output buffer power supply for reduced noise, crosstalk and jitter. input clock frequency standard 14.31

C5002_International.pdf