CD4517BMS - CMOS Dual 64-Stage Static Shift Register
CD4517BMS dual 64-stage static shift register consists of two independent registers each having a clock, data, and write enable input and outputs accessible at taps following the 16th, 32rd, 48th, and 64th stages.
These taps also serve as input points allowing data to be inputted at the 17th, 33rd,
CD4517BMS Features
* High-Voltage Types (20-Volt Rating)
* Low Quiescent Current - 10nA/pkg (Typ.) at VDD = 5V
* Clock Frequency 12MHz (Typ.) at VDD = 10V
* Schmitt Trigger Clock Inputs Allow Operation with Very Slow Clock Rise and Fall Times
* Capable of Driving Two Low-power T
