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LMS12JC35 12-bit Cascadable Multiplier

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Description

LMS12 DEVICES INCORPORATED 12-bit Cascadable Multiplier-Summer LMS12 DEVICES INCORPORATED 12-bit Cascadable Multiplier-Summer .
The LMS12 is a high-speed 12 x 12-bit combinatorial multiplier integrated with a 26-bit adder in a single 84-pin package.

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Datasheet Specifications

Part number
LMS12JC35
Manufacturer
LOGIC Devices Incorporated
File Size
195.44 KB
Datasheet
LMS12JC35_LOGICDevicesIncorporated.pdf
Description
12-bit Cascadable Multiplier

Features

* are discussed individually in the following paragraphs. MULTIPLIER The A11-0 and B11-0 inputs to the LMS12 are captured at the rising edge of the clock in the 12-bit A and B input registers, respectively. These registers are independently enabled by the ENA and ENB inputs. The registered input data

Applications

* The LMS12 implements the general form (A

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