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LMU112

12 x 12-bit Parallel Multiplier

LMU112 Features

* u u u u 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned Operands u Three-State Outputs u Package Styles Available:

* 48-pin PDIP

* 52-pin PLCC, J-Lead LMU112 BLOCK DIAGRAM A 11-0 12 CLK A CLK B A REGISTER TC B 11-0 12

LMU112 General Description

The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K. The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A.

LMU112 Datasheet (46.51 KB)

Preview of LMU112 PDF

Datasheet Details

Part number:

LMU112

Manufacturer:

LOGIC Devices Incorporated

File Size:

46.51 KB

Description:

12 x 12-bit parallel multiplier.

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TAGS

LMU112 12-bit Parallel Multiplier LOGIC Devices Incorporated

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