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LMU112 12 x 12-bit Parallel Multiplier

LMU112 Description

LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier LMU112 DEVICES INCORPORATED 12 x 12-bit Parallel Multiplier .
The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology.

LMU112 Features

* u u u u 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned Operands u Three-State Outputs u Package Styles Available:
* 48-pin PDIP
* 52-pin PLCC, J-Lead LMU112 BLOCK DIAGRAM A 11-0 12 CLK A CLK B A REGISTER TC B 11-0 12

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Datasheet Details

Part number
LMU112
Manufacturer
LOGIC Devices Incorporated
File Size
46.51 KB
Datasheet
LMU112_LOGICDevicesIncorporated.pdf
Description
12 x 12-bit Parallel Multiplier

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12-bit Parallel Multiplier LOGIC Devices Incorporated
LOGIC Devices Incorporated LMU112-like datasheet