LMU112 Datasheet - LOGIC Devices Incorporated

LMU112 12 x 12-bit Parallel Multiplier

The LMU112 is a high-speed, low power 12-bit parallel multiplier built using advanced CMOS technology. The LMU112 is pin and functionally compatible with Fairchilds’s MPY112K. The A and B input operands are loaded into their respective registers on the rising edge of the separate clock inputs (CLK A.

LMU112 Features

* u u u u 25 ns Worst-Case Multiply Time Low Power CMOS Technology Replaces Fairchild MPY112K Two’s Complement or Unsigned Operands u Three-State Outputs u Package Styles Available:

* 48-pin PDIP

* 52-pin PLCC, J-Lead LMU112 BLOCK DIAGRAM A 11-0 12 CLK A CLK B A REGISTER TC B 11-0 12

LMU112 Datasheet (46.51 KB)