LMU217 Datasheet - LOGIC Devices Incorporated

LMU217 16 x 16-bit Parallel multiplier

The LMU217 is a high-speed, low RND is loaded on the rising edge of power 16-bit parallel multiplier. CLK, provided either ENA or ENB are LOW. RND, when HIGH, adds ‘1’ to The LMU217 produces the 32-bit prodthe most significant bit position of the uct of two 16-bit numbers. Data present least signifi.

LMU217 Features

* u 25 ns Worst-Case Multiply Time u Low Power CMOS Technology u Replaces Cypress CY7C517, IDT 7217L, and AMD Am29517 u Single Clock Architecture with Register Enables u Two’s Complement, Unsigned, or Mixed Operands u Three-State Outputs u 68-pin PLCC, J-Lead LMU217 BLOCK DIAGRAM TCA CLK ENA ENB For

LMU217_LOGICDevicesIncorporated.pdf