MX30UF4G18AB - 4G-bit NAND Flash Memory
7 Figure 1.
Logic Diagram 7 2-1.
ORDERING INFORMATION8 3.
PIN CONFIGURATIONS10 3-1.
PIN DESCRIPTIONS13 4.
BLOCK DIAGRAM15 5.
SCHEMATIC CELL LAYOUT AND ADDRESS ASSIGNMENT16 Table 1-1.
Address Allocation (for x8) 16 Table 1-2.
Address Allocation (for x16) 16 6.
DEVICE OPERATIONS17 6-1.
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