MHS30C7202N Datasheet - MagnaChip

MHS30C7202N Highly Integrated MPU

HMS30C7202N Copyright. 2004 MagnaChip Semiconductor Ltd. ALL RIGHTS RESERVED. No part of this publication may be copied in any form, by photocopy, microfilm, retrieval system, or by any other means now known or hereafter invented without the prior written permission of MagnaChip Semiconductor Ltd. MagnaChip Semiconductor Ltd. #1, Hyangjeong-dong, Heungduk-gu, Cheongju-si, Chungcheongbuk-do, Republic of Korea Homepage: www.MagnaChip.com Technical Support Homepage: www.softonchip.com H.Q. of M.

MHS30C7202N Features

* 32-bit ARM7TDMI RISC static CMOS CPU core : Running up to 70 MHz 8Kbytes combined instruction/data cache Memory management unit Supports Little Endian operating system 2Kbytes SRAM for internal buffer memory On-chip peripherals with individ

MHS30C7202N Datasheet (2.05 MB)