* Optional Configuration via Serial EEPROM Inter- face
* Supports 8, 16 and 32 Bit CPU Accesses
* Internal 32 Bit Wide Data Path (Into Packet Buffer Memory)
* Built-in Transparent Arbitration for Slave Sequen- tial Access Architecture
* Flat MMU Architecture w
LAN91C111 Datasheet (736.70 KB)
LAN91C111
736.70 KB
10/100 non-pci ethernet single chip mac + phy.
LAN91C111 10/100 Non-PCI Ethernet Single Chip MAC + PHY Highlights Single Chip Ethernet Controller Dual Speed - 10/100 Mbps <.
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