Features
* C Compiler Optimized RISC Architecture
* Operating Speed:
* DC
* 32 MHz clock input
* 125 ns minimum instruction time
* 16-Level Deep Hardware Stack
* Low-Current Power-on Reset (POR)
* Configurable Power-up Timer (PWRT)
* Br
Applications
* This product family is available from 8 to 44-pin packages in a memory range of 7 KB to 28 KB, with speeds up to 32 MHz. This product includes a 12-bit differential Analog-to-Digital Converter with Computation (ADCC), two 8-bit Digital-to-Analog Converters (DAC), a 16-bit Pulse-Width Modulation (PW
