Description
The 4 Meg x 4 DRAM is a randomly accessed, solid-state memory containing 16,777,216 bits organized in a x4 configuration.
Rev.
Features
- Industry-standard x4 pinout, timing, functions and packages.
- State-of-the-art, high-performance, low-power CMOS silicon-gate process.
- Single power supply (+3.3V ±0.3V or +5V ±10%).
- All inputs, outputs and clocks are TTL-compatible.
- Refresh modes: RAS#-ONLY, HIDDEN and CAS#BEFORE-RAS# (CBR).
- Optional Self Refresh (S) for low-power data retention.
- 11 row, 11 column addresses (2K refresh) or 12 row, 10 column addresses (4K refresh).
MT4C4M4Ex_MicronTechnology.pdf
