Datasheet4U Logo Datasheet4U.com

M2S12D30TP-75L Datasheet - Mitsubishi

M2S12D30TP-75L 512M Double Data Rate Synchronous DRAM

M2S12D20TP is a 4-bank x 33,554,432-word x 4-bit, M2S12D30TP is a 4-bank x 16,777,216-word x 8-bit, double data rate synchronous DRAM, with SSTL_2 interface. All control and address signals are referenced to the rising edge of CLK. Input data is registered on both edges of data strobes, and output d.

M2S12D30TP-75L Features

* - Vdd=Vddq=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs (CLK and /CLK) - DLL aligns DQ and DQS transitions - Commands are entered on each positive CLK edge; - data and da

M2S12D30TP-75L Datasheet (754.04 KB)

Preview of M2S12D30TP-75L PDF

Datasheet Details

Part number:

M2S12D30TP-75L

Manufacturer:

Mitsubishi

File Size:

754.04 KB

Description:

512m double data rate synchronous dram.

📁 Related Datasheet

M2S12D30TP-75 512M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S12D30TP-10 512M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S12D30TP-10L 512M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S12D30TP 512M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S12D20TP 512M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S12D20TP-10 512M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S12D20TP-10L 512M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S12D20TP-75 512M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S12D20TP-75L 512M Double Data Rate Synchronous DRAM (Mitsubishi)

M2S1G64CBH4B5P Unbuffered DDR3 SO-DIMM (Nanya)

TAGS

M2S12D30TP-75L 512M Double Data Rate Synchronous DRAM Mitsubishi

Image Gallery

M2S12D30TP-75L Datasheet Preview Page 2 M2S12D30TP-75L Datasheet Preview Page 3

M2S12D30TP-75L Distributor