M2S56D20ATP-10 Datasheet, Dram, Mitsubishi

M2S56D20ATP-10 Features

• Dram - VDD=VDDQ=2.5V+0.2V - Double data rate architecture; two data transfers per clock cycle - Bidirectional, data strobe (DQS) is transmitted/received with data - Differential clock inputs

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M2S56D20ATP-10

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Mitsubishi

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📄 Datasheet

Description:

256m double data rate synchronous dram. M2S56D20ATP / AKT is a 4-bank x 16777216-word x 4-bit, M2S56D30ATP / AKT is a 4-bank x 8388608-word x 8-bit, M2S56D40ATP/ AKT is a 4-

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M2S56D20ATP-10

Mitsubishi

📁 Related Datasheet

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M2S56D20ATP-75A - 256M Double Data Rate Synchronous DRAM (Mitsubishi)
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M2S56D20ATP-75L - 256M Double Data Rate Synchronous DRAM (Mitsubishi)
DDR SDRAM (Rev.1.44) Mar. '02 MITSUBISHI LSIs M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L.

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M2S56D20AKT - 256M Double Data Rate Synchronous DRAM (Mitsubishi)
DDR SDRAM (Rev.1.0) Jul. '01 Preliminary M2S56D20/ 30/ 40AKT MITSUBISHI LSIs 256M Double Data Rate Synchronous DRAM PRELIMINARY Some of contents a.

M2S56D20AKT-10 - 256M Double Data Rate Synchronous DRAM (Mitsubishi)
DDR SDRAM (Rev.1.44) Mar. '02 MITSUBISHI LSIs M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L.

M2S56D20AKT-10L - 256M Double Data Rate Synchronous DRAM (Mitsubishi)
DDR SDRAM (Rev.1.44) Mar. '02 MITSUBISHI LSIs M2S56D20/ 30/ 40ATP -75AL, -75A, -75L, -75, -10L, -10 M2S56D20/ 30/ 40AKT -75AL, -75A, -75L, -75, -10L.