M2V56S20TP Datasheet - Mitsubishi

M2V56S20TP 256M Synchronous DRAM

M2V56S20TP is a 4-bank x 16777216-word x 4-bit, M2V56S30TP is a 4-bank x 8388608-word x 8-bit, M2V56S40TP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40TP achieve very high speed data ra.

M2V56S20TP Features

* - Single 3.3v±0.3V power supply - Max. Clock frequency 100MHz(-7/-8), 133MHz (-6) - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/4/8/full page (programmab

M2V56S20TP_MitsubishiElectricSemiconductor.pdf