* - Single 3.3v±0.3V power supply - Max. Clock frequency -5:PC166 / -6:PC133 / -7:PC100 - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/
M2V56S30AKT Datasheet (620.06 KB)
M2V56S30AKT
Mitsubishi
620.06 KB
256m synchronous dram.
SDRAM (Rev.1.01) Single Data Rate July '01 MITSUBISHI LSIs M2V56S20/ 30/ 40 AKT -5, -6, -7 256M Synchronous DRAM Some of contents are subject to ch.
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