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M2V56S30ATP

256M Synchronous DRAM

M2V56S30ATP Features

* - Single 3.3v±0.3V power supply - Max. Clock frequency -5:PC166 / -6:PC133 / -7:PC100 - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/

M2V56S30ATP General Description

M2V56S20ATP is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40ATP achieve very high speed dat.

M2V56S30ATP Datasheet (619.17 KB)

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Datasheet Details

Part number:

M2V56S30ATP

Manufacturer:

Mitsubishi

File Size:

619.17 KB

Description:

256m synchronous dram.
SDRAM (Rev.1.01) Single Data Rate Jul '01 MITSUBISHI LSIs M2V56S20/ 30/ 40 ATP -5, -6, -7 256M Synchronous DRAM Some of contents are subject to cha.

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M2V56S40ATP - 256M Synchronous DRAM (Mitsubishi)
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M2V56S40TP - 256M Synchronous DRAM (Mitsubishi)
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M2V56S30ATP 256M Synchronous DRAM Mitsubishi

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