M2V56S40ATP Datasheet - Mitsubishi

M2V56S40ATP 256M Synchronous DRAM

M2V56S20ATP is a 4-bank x 16777216-word x 4-bit, M2V56S30ATP is a 4-bank x 8388608-word x 8-bit, M2V56S40ATP is a 4-bank x 4194304-word x 16-bit, synchronous DRAM, with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. The M2V56S20/30/40ATP achieve very high speed dat.

M2V56S40ATP Features

* - Single 3.3v±0.3V power supply - Max. Clock frequency -5:PC166 / -6:PC133 / -7:PC100 - Fully Synchronous operation referenced to clock rising edge - Single Data Rate - 4 bank operation controlled by BA0, BA1 (Bank Address) - /CAS latency- 2/3 (programmable) - Burst length- 1/2/

M2V56S40ATP_MitsubishiElectricSemiconductor.pdf