M2V64S30DTP-7L Datasheet - Mitsubishi

M2V64S30DTP-7L 64M Synchronous DRAM

M 2V64S20DTP is a 4-bank x 4,194,304-word x 4-bit, M 2V64S30DTP is a 4-bank x 2,097,152-word x 8-bit, M 2V64S40DTP is a 4-bank x 1,048,576-word x 16-bit, synchronous DRAM , with LVTTL interface. All inputs and outputs are referenced to the rising edge of CLK. M 2V64S20DTP, M 2V64S30DTP and M 2V64S40.

M2V64S30DTP-7L Features

* M2V64S20/30/40DTP ITEM tCLK tRAS tRCD tAC tRC Icc1 Clock Cycle T ime Active to Precharge Command Period Row to Column Delay Access Time from CLK Ref /Active Command Period Operation Current (Max.) (Single Bank) (Min.) (Min.) (Min.) (Max.) (CL=3) (Min.) V64S20D V64S30D V64S40D Icc6 Self Refresh Curre

M2V64S30DTP-7L_MitsubishiElectricSemiconductor.pdf