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M5M4V4405CJ - EDO (HYPER PAGE MODE) 4M-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM

Datasheet Summary

Description

This is a family of 1048576-word by 4-bit dynamic RAMS, fabricated with the high performance CMOS process,and is ideal for large-capacity memory systems where high speed, low power dissipation , and low costs are essential.

Features

  • Type name M5M4V4405CXX-6, -6S M5M4V4405CXX-7, -7S A0 9 RAS CAS Address OE Cycle Power dissipaaccess access access access tion time time time time time (max. ns) (max. ns) (max. ns) (max. ns) (min. ns) (typ. mW) A1 10 A2 11 A3 12 VCC 13 18 A8 17 A7 16 A6 15 A5 14 A4 60 70 15 20 30 35 15 20 110 130 264 231 XX=J, TP Standard 26 pin SOJ, 26 pin TSOP(II) Single 3.3V±0.3V supply Low stand-by power dissipation CMOS lnput level 1.8mW(Max).
  • CMOS lnput level 180µW(Max) Low operating power dissipat.

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Datasheet Details

Part number M5M4V4405CJ
Manufacturer Mitsubishi
File Size 293.68 KB
Description EDO (HYPER PAGE MODE) 4M-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
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Other Datasheets by Mitsubishi
  • M5M4V4405CJ-6 - EDO (HYPER PAGE MODE) 4M-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
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  • M5M4V4405CJ-7 - EDO (HYPER PAGE MODE) 4M-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
  • M5M4V4405CJ-7S - EDO (HYPER PAGE MODE) 4M-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
  • M5M4V4405CTP-6 - EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
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  • M5M4V4405CTP-7 - EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM
  • M5M4V4405CTP-7S - EDO (HYPER PAGE MODE) 4194304-BIT(1048576-WORD BY 4-BIT) DYNAMIC RAM

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MITSUBISHI LSIsLSIs MITSUBISHI M5M4V4405CJ,TP-6,-7,-6S,-7S M5M4V4405CJ,TP-6,-7,-6S,-7S EDO EDO (HYPER (HYPER PAGE PAGE MODE) MODE) 4194304-BIT 4194304-BIT(1048576-WORD (1048576-WORD BY BY 4-BIT) 4-BIT) DYNAMIC DYNAMIC RAM RAM DESCRIPTION This is a family of 1048576-word by 4-bit dynamic RAMS, fabricated with the high performance CMOS process,and is ideal for large-capacity memory systems where high speed, low power dissipation , and low costs are essential. The use of quadruple-layer polysilicon process combined with silicide technology and a single-transistor dynamic storage stacked capacitor cell provide high circuit density at reduced costs. Multiplexed address inputs permit both a reduction in pins and an increase in system densities.
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