M5M5Y5672TG-25 Datasheet - Mitsubishi

M5M5Y5672TG-25 - 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit.

It is designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads.

Mitsubishi's SRAMs are fabricated with high performance, low power CMOS technology, pro

2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification.

Some parametric limits are subject to change.

M5M5Y5672TG 25,22,20 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM Synchronous circuitry allows for precise cycle control triggered by a positive edge clock transition.

Synchronous signals include : all Addresses, all Data Inputs, all Chip Enables (E1#, E2, E3), Address Advance/Load (ADV), Byte Write Enables (BWa#, BWb#, BWc#, BWd#, BWe#, BW

M5M5Y5672TG-25 Features

* Fully registered inputs and outputs for pipelined operation

* Fast clock speed: 250, 225, and 200 MHz

* Fast access time: 2.6, 2.8, 3.2 ns

* Single 1.8V +150/-100mV power supply VDD

* Separate VDDQ for 1.8V I/O

* Individual byte write (BWa# - BWh#) c

M5M5Y5672TG-25_MitsubishiElectricSemiconductor.pdf