M5M5Y5672TG-25 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Mitsubishi

Description

2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification.Some parametric limits are subject to change.M5M5Y5.
The M5M5Y5672TG is a family of 18M bit synchronous SRAMs organized as 262144-words by 72-bit.

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Datasheet Specifications

Part number: M5M5Y5672TG-25
Manufacturer: Mitsubishi
File Size: 240.05 KB
Datasheet: M5M5Y5672TG-25_MitsubishiElectricSemiconductor.pdf
Description: 18874368-BIT(262144-WORD BY 72-BIT) NETWORK SRAM

Features

* Fully registered inputs and outputs for pipelined operation
* Fast clock speed: 250, 225, and 200 MHz
* Fast access time: 2.6, 2.8, 3.2 ns
* Single 1.8V +150/-100mV power supply VDD
* Separate VDDQ for 1.8V I/O
* Individual byte write (BWa# - BWh#) c

Applications

* The sense of two User-Programmable Chip Enable inputs (E2, E3), whether they function as active LOW or active HIGH inputs, is determined by the state of the programming inputs, EP2 and EP3. The Linear Burst order (LBO#) is DC operated pin. LBO# pin will allow the choice of either an interleaved bur

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M5M5Y5672TG-25 18874368-BIT262144-WORD 72-BIT NETWORK SRAM Mitsubishi

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