V54C365324V Datasheet - Mosel Vitelic Corp

V54C365324V 3.3 VOLT ULTRA HIGH PERFORMANCE 2M X 32 SDRAM

The V54C365324V is a 67,108, 864 bits synchronous high data rate DRAM organized as 4 x 524,288 words by 32 bits. The device is designed to comply with JEDEC standards set for synchronous DRAM products, both electrically and mechanically. Synchronous design allows precise cycle control with the syste.

V54C365324V Features

* s JEDEC Standard 3.3V Power Supply s The V54C365324V is ideally suited for high performance graphics peripheral applications s Single Pulsed RAS Interface s Programmable CAS Latency: 2, 3 s All Inputs are sampled at the positive going edge of clock s Programmable Wrap Sequence: Sequential or Interle

V54C365324V Datasheet (353.92 KB)