V54C365164VL, V54C365164VD Datasheet - Mosel Vitelic

V54C365164VL 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM

The V54C365164VD(L) is a four bank Synchronous DRAM organized as 4 banks x 1Mbit x 16. The V54C365164VD(L) achieves high speed data transfer rates up to 225 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the control, .

w w w . D a t a S h e e t 4 U . c o m MOSEL VITELIC V54C365164VD(L) HIGH PERFORMANCE 225/200/166/143 MHz 3.3 VOLT 4M X 16 SYNCHRONOUS DRAM 4 BANKS X 1Mbit X 16 PRELIMINARY 45 System Frequency (fCK) Clock Cycle Time (tCK3) Clock Access Time (tAC3) CAS Latency = 3 Clock Access Time (tAC2) CAS Latency = 2 Clock Access Time (tAC1) CAS Latency = 1 225 MHz 4.5 ns 4.5 ns 4.5 ns 12 ns 5 200 MHz 5 ns 5 ns 5 ns 12 ns 6 166 MHz 6 ns 5.4 ns 5.5 ns 12 ns 7 143 MHz 7 ns 5.4 ns 5.5 ns .

V54C365164VL Features

* s 4 banks x 1Mbit x 16 organization s High speed data transfer rates up to 225 MHz s Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge s Single Pulsed RAS Interface s Data Mask for byte Control s Four Banks controlled by BA0 & BA1 s Programmable CAS Latency: 1, 2, 3 s Pr

V54C365164VD_MoselVitelic.pdf