DSP56F802 - DSP56F802 16-bit Digital Signal Processor
* * * * * * Computer-Operating Properly (COP) watchdog timer External interrupts via GPIO Trimmable on-chip relaxation oscillator External reset pin for hardware reset JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugg
DSP56F802/D Rev.
0, 1/2002 DSP56F802 Preliminary Technical Data DSP56F802 16-bit Digital Signal Processor Up to 40 MIPS operation at 80 MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes 8K × 16-bit words Program Flash 1K × 16-bit words Program RAM 2K × 16-bit words Data Flash 1K × 16-bit words Data RAM 2K × 16-b
DSP56F802 Features
* 1.1.1
* Digital Signal Processing Core Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture As many as 40 Million Instructions Per Second (
