Description
Four General Purpose Quad Timers: Timer A (sharing pins with Quad Dec0), Timers B &C without external pins and Timer D with two pins CAN 2.0 B module with 2-pin ports for transmit and receive Serial Communica
Features
- 1.1.1.
- Digital Signal Processing Core
Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators, including extension bits 16-bit bidirectional barrel shifter Parallel instruction set with unique DSP addressing modes Hardware DO and REP loops Three internal a.
DSP56F803 Datasheet
