Description
Computer-Operating Properly (COP) watchdog timer External interrupts via GPIO Trimmable on-chip relaxation oscillator External reset pin for hardware reset JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugg
Features
- 1.1.1.
- Digital Signal Processing Core
Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction.
DSP56F802 Datasheet
