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DSP56F802 - DSP56F802 16-bit Digital Signal Processor

General Description

Computer-Operating Properly (COP) watchdog timer External interrupts via GPIO Trimmable on-chip relaxation oscillator External reset pin for hardware reset JTAG/On-Chip Emulation (OnCE™) for unobtrusive, processor speed-independent debugg

Key Features

  • 1.1.1.
  • Digital Signal Processing Core Efficient 16-bit DSP56800 family DSP engine with dual Harvard architecture As many as 40 Million Instructions Per Second (MIPS) at 80 MHz core frequency Single-cycle 16 × 16-bit parallel Multiplier-Accumulator (MAC) Two 36-bit accumulators including extension bits 16-bit bidirectional barrel shifter Parallel instruction.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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DSP56F802/D Rev.