74LS273 Datasheet (Motorola) - OCTAL D FLIP-FLOP

74LS273, OCTAL D FLIP-FLOP

The SN54 / 74LS273 is an 8-Bit Parallel Register with a common Clock and common Master Reset.

When the MR input is LOW, the Q outputs are LOW, independent of the other inputs.

Information meeting the setup and hold time requirements of the D inputs is transferred to the Q outputs on the LOW-to-HIGH

OCTAL D FLIP-FLOP WITH CLEAR The SN54 / 74LS273 is a high-speed 8-Bit Register.

The register consists of eight D-Type Flip-Flops with a Common Clock and an asynchronous active LOW Master Reset.

This device is supplied in a 20-pin package featuring 0.3 inch lead spacing.

SN54/74LS273 8-Bit High Speed Register Parallel Register Common Clock and Master Reset Input Clamp Diodes Limit High-Speed Termination Effects CONNECTION DIAGRAM DIP (TOP VIEW) VCC 20 Q7