F801FA60 Datasheet - Motorola

F801FA60 DSP56F801FA60

* * * * * * Eleven multiplexed General Purpose I/O (GPIO) pins Computer-Operating Properly (COP) watchdog timer One dedicated external interrupt pin External reset pin for hardware reset Emulation (OnCE™) for unobtrusive, processor speed-independent .

Freescale Semiconductor, Inc. DSP56F801/D Rev. 13.0, 02/2004 56F801 www.datasheet4u.com Technical Data 56F801 16-bit Hybrid Controller Up to 30 MIPS operation at 60MHz core frequency Up to 40 MIPS operation at 80MHz core frequency DSP and MCU functionality in a unified, C-efficient architecture MCU-friendly instruction set supports both DSP and controller functions: MAC, bit manipulation unit, 14 addressing modes Hardware DO and REP loops 6-channel PWM Module Two 4-channel.

F801FA60 Features

* www.datasheet4u.com 1.1.1

* Digital Signal Processing Core Efficient 16-bit 56800 family hybrid controller engine with dual Harvard architecture As many as 40

F801FA60_Motorola.pdf