MC88915TFN100 Datasheet - Motorola

MC88915TFN100 LOW SKEW CMOS PLL CLOCK DRIVER

on page 11). Pulling the OE/RST pin low puts the clock outputs 2X_Q, Q0 *Q4, Q5 and Q/2 into a high impedance state (3 *state). After the OE/RST pin goes back high Q0 *Q4, Q5 and Q/2 will be reset in the low state, with 2X_Q being the inverse of the selected SYNC input. Assuming.

MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC88915TFN55 MC88915TFN70 MC88915TFN100 MC88915TFN133 MC88915TFN160 Low Skew CMOS PLL Clock Drivers, 3-State 55, 70, 100, 133 and 160MHz Versions The MC88915T Clock Driver utilizes phase locked loop technology to lock its low skew outputs’ frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance PC’s and workstations. For a 3.3V version, see the MC88LV915T data sheet. The PLL allows the hi.

MC88915TFN100 Features

* Five Outputs (Q0

* Q4) with Output

* Output Skew < 500 ps each being phase and frequency locked to the SYNC input

* The phase variation from part

* to

* part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which

MC88915TFN100_MotorolaInc.pdf