MC88915TFN100 Datasheet - Motorola

MC88915TFN100, LOW SKEW CMOS PLL CLOCK DRIVER

MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC88915TFN55 MC88915TFN70 MC88915TFN100 MC88915TFN133 MC88915TFN160 Low Skew CMOS PLL Clock Drivers, 3-State 5.
on page 11). Q4, Q5 and Q/2 into a high impedance state (3. state).

Features

* Five Outputs (Q0
* Q4) with Output
* Output Skew < 500 ps each being phase and frequency locked to the SYNC input
* The phase variation from part
* to
* part between the SYNC and FEEDBACK inputs is less than 550 ps (derived from the tPD specification, which

Applications

* when a central system clock must be distributed synchronously to multiple boards (see Figure 7). LOW SKEW CMOS PLL CLOCK DRIVER Five “Q” outputs (Q0
* Q4) are provided with less than 500 ps skew between their rising edges. The Q5 output is inverted (180° phase shift) from the “Q” outputs. Th

MC88915TFN100_MotorolaInc.pdf