MCM63F819K - (MCM63F737K / MCM63F819K) 128K x 36 and 256K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM
Pin Locations 85 Symbol ADSC Type Input Description Synchronous Address Status Controller: Active low, interrupts any ongoing burst and latches a new external address.
Used to initiate a READ, WRITE, or chip deselect.
Synchronous Address Status Processor: Active low, interrupts any ongoing burst an
MOTOROLA Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA Order this document by MCM63F737K/D Advance Information 128K x 36 and 256K x 18 Bit Flow Through BurstRAM Synchronous Fast Static RAM The MCM63F737K and MCM63F819K are 4M bit synchronous fast static RAMs designed to provide a burstable, high performance, secondary cache.
The MCM63F737K (organized as 128K words by 36 bits) and the MCM63F819K (organized as 256K words by 18 bits) integrate input registers, a 2<
MCM63F819K Features
* pt G, LBO, and ZZ. Linear Burst Order Input: This pin must remain in steady state (this signal not registered or latched). It must be tied high or low. Low
* linear burst counter. High
* interleaved burst counter. Synchronous Address Inputs: These inputs are reg
