MCM69F536C Datasheet (Motorola) - 32K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

MCM69F536C, 32K x 36 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE, or chip deselect cycle.

Synchronous Address Status Processor: Initiates READ, WRITE, or chip deselect cycle (exception * chip deselect does not occur when ADSP is

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69F536C/D 32K x 36 Bit Flow Through BurstRAM Synchronous Fast Static RAM The MCM69F536C is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, 486, i960™, and Pentium™ microprocessors.

It is organized as 32K words of 36 bits each.

This device integrates input registers, a 2 bit address counter, and high speed SRAM onto a sing

MCM69F536C Features

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* 55 to 125 Unit V V mA W °C °C This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this h