MCM69F618C Datasheet (Motorola) - 64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

MCM69F618C, 64K x 18 Bit Flow-Through BurstRAM Synchronous Fast Static RAM

Pin Locations 85 84 Symbol ADSC ADSP Type Input Input Description Synchronous Address Status Controller: Initiates READ, WRITE or chip deselect cycle.

Synchronous Address Status Processor: Initiates READ, WRITE or chip deselect cycle (exception * chip deselect does not occur when ADSP is as

MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order this document by MCM69F618C/D 64K x 18 Bit Flow Through BurstRAM Synchronous Fast Static RAM The MCM69F618C is a 1M bit synchronous fast static RAM designed to provide a burstable, high performance, secondary cache for the 68K Family, PowerPC™, 486, i960™, and Pentium™ microprocessors.

It is organized as 64K words of 18 bits each.

This device integrates input registers, a 2 bit address counter, and high speed SRAM onto a sing

MCM69F618C Features

* dvised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high

* impedance circuit. NOTES: 1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to RECOMMENDED