MSC8101 Datasheet (Motorola) - Network Digital Signal Processor

MSC8101, Network Digital Signal Processor

3-1 Lidded FC-PBGA Package Mechanical Drawing 3-31 Thermal Design Considerations 4-1 Electrical Design Considerations 4-1 Power Considerations 4-2 Layout Practices 4-3 Chapter 2 Physical and Electrical Specifications 2.1 2.2 2.3 2.4 2.5 2.6 Chapter 3 Packaging 3.1 3.2 Chapter 4 Design Consid

Freescale Semiconductor Technical Data MSC8101 Rev.

16, 11/2004 MSC8101 Network Digital Signal Processor CPM MCC / UART / HDLC / Transparent / Ethernet / Fast Ethernet / ATM / SCC 3 × FCC 2 × MCC 4 × SCC 2 × SMC SPI I2C UTOPIA Interface MII Interrupt Controller Timers Parallel I/O Baud Rate Generators Dual Ported RAM Bridge 2 × SDMA RISC 64-bit Local Bus MEMC DMA Engine SIU 64-bit System Bus MEMC PIT System Protection Reset Control Clock Control SIC_EXT Interrupts SIC 64/32-bit System Bus TDM

MSC8101 Features

* iii Target Applications iv Product Documentation iv Chapter 1 Signals/Connections 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Power Signals 1-4 Clock Signals 1-4 Reset, Configuration, and EOnCE Event Signals 1-5 System Bus, HDI16, and Interrupt Signals 1-6 Memory Controller Signals 1-13 CPM Ports 1-15 JTA