Description
The logic diagram and truth table indicate the functional characteristics of the SN54/74LS323 Universal Shift/Storage Register..
Features
- are described below:
1. They use eight D-type edge-triggered flip-flops that respond only to the LOW-to-HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control (S0, S1) and data inputs (DS0, DS7, I/O0.
- I/O7) may be stable at least a setup time prior to the positive transition of the Clock Pulse. 2. When S0 = S1 = 1, I/O0.
- I/O7 are parallel inputs to flip-flops Q0.
- Q7 respectively, and the outputs of Q0.
- Q7 are in the high i.
