D720133 - UPD720133
6 Preliminary Data Sheet S17100EJ2V0DS µPD720133 2.2 Pin Setting Settings of the SCL, SDA and unused pins (TEST and SCAN) are recommended as follows. Please note that the setting of the SCL depends on size of Serial ROM. Table 2-2. Pin Settings Pin Name SCL SDA TEST SCAN Pull Up Pull Up Low Clam.
PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD720133 USB2.0 to IDE Bridge The µPD720133 is designed to function as a bridge between USB 2.0 and ATA/ATAPI. The µPD720133 complies with the Universal Serial Bus Specification Revision 2.0 full-/high-speed signaling and works up to 480 Mbps. The µPD720133 consists of a CISC processor, an ATA/ATAPI controller, an endpoint controller (EPC), a serial interface engine (SIE), and an USB2.0 transceiver. The USB2.0 protocol and class specific protoco.
D720133 Features
* Compliant with Universal Serial Bus Specification Revision 2.0 (Data Rate 12/480 Mbps)
* Compliant with ATA/ATAPI-6 (LBA48, PIO Mode 0-4, Multi Word DMA Mode 0-2, Ultra DMA Mode 0-4)
* USB2.0 high-speed bus powered device capability
* Certified by USB implementers f
