UPD4564323 Datasheet - NEC

UPD4564323 - 64M-bit Synchronous DRAM 4-bank/ LVTTL

The µPD4564323 is a high-speed 67,108,864-bit synchronous dynamic random-access memory, organized as 524,288 words × 32 bits × 4 banks. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock.

UPD4564323 Features

* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

* Pulsed interface

* Possible to assert random column address in every cycle

* Quad internal banks controlled by BA0 and BA1 (Bank Select)

* ×32 organization

* Byte c

UPD4564323_NEC.pdf