74AHCT132 Datasheet - NXP

Quad 2-input NAND Schmitt trigger

74AHCT132 Features

* ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V; MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V

* Balanced propagation delays

* Inputs accepts voltages higher than VCC

* For AHC only: operates with CMOS input levels

* For AHCT onl

74AHCT132 General Description

The 74AHC/AHCT132 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC/AHCT132 contain four 2-input NAND gates which accept standard input signals. They are capable of transforming slowl.

74AHCT132 Datasheet (106.13 KB)

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74AHCT132

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NXP ↗

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106.13 KB

Description:

Quad 2-input nand schmitt trigger.
INTEGRATED CIRCUITS DATA SHEET 74AHC132; 74AHCT132 Quad 2-input NAND Schmitt trigger Product speciﬁcation Supersedes data of 1999 May 31 File under .

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74AHCT132 Quad 2-input NAND Schmitt trigger NXP

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74AHCT132 Features

74AHCT132 General Description

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