74AHCT30 Datasheet - NXP

74AHCT30 8-input NAND gate

74AHC30; 74AHCT30 The 74AHC/AHCT30 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. The 74AHC/AHCT30 provide the 8-input NAND function. TYPICAL SYMBOL tPHL/tPLH CI CO CPD Notes 1. CPD is us.

74AHCT30 Features

* ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V

* Balanced propagation delays

* Inputs accept voltages higher than VCC

* For AHC only: operates with CMOS input levels

* For AHCT only:

74AHCT30_PhilipsSemiconductors.pdf