74AHCT373 Datasheet - NXP

74AHCT373 Octal D-type transparent latch

The 74AHC/AHCT373 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard no. 7A. QUICK REFERENCE DATA Ground = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. 74AHC373; 74AHCT373 The 74AHC/AHCT373 are octal D-type t.

74AHCT373 Features

* ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V

* Balanced propagation delays

* All inputs have Schmitt-trigger actions

* Inputs accepts voltages higher than VCC

* Common 3-state outp

74AHCT373_PhilipsSemiconductors.pdf