74AHCT374PW Description
74AHC374; 74AHCT374 Octal D-type flip-flop; positive edge-trigger; 3-state Rev.03 * 12 June 2008 Product data sheet 1.General .74AHCT374PW Features
* I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept voltages higher than VCC I Common 3-state output enable input I Input levels: N For 74AHC374: CMOS level N For 74AHCT374: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A e74AHCT374PW Applications
* A clock input (CP) and an output enable input (OE) are common to all flip-flops. The eight flip-flops will store the state of their individual D inputs that meet the set-up and hold times requirements for the LOW-to-HIGH CP transition. When OE is LOW the content of the eight flip-flops is available at th
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