74AUP1G240 Low-power inverting buffer/line driver

NXP

Description

www.DataSheet4U.com 74AUP1G240 Low-power inverting buffer/line driver; 3-state Rev.01 * 6 November 2006 Product data sheet 1.General descr.
The 74AUP1G240 is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families.

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Datasheet Specifications

Part number: 74AUP1G240
Manufacturer: NXP ↗
File Size: 125.27 KB
Datasheet: 74AUP1G240_PhilipsSemiconductors.pdf
Description: Low-power inverting buffer/line driver

Features

* s Wide supply voltage range from 0.8 V to 3.6 V s High noise immunity s Complies with JEDEC standards: x JESD8-12 (0.8 V to 1.3 V) x JESD8-11 (0.9 V to 1.65 V) x JESD8-7 (1.2 V to 1.95 V) x JESD8-5 (1.8 V to 2.7 V) x JESD8-B (2.7 V to 3.6 V) s ESD protection: x HBM JESD22-A114-D exceeds 5000 V x MM

Applications

* using IOFF. The IOFF circuitry disables the output, preventing the damaging backﬂow current through the device when it is powered down. The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level

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74AUP1G240 Low-power inverting buffer line driver NXP

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