* DRAM signal timing generator
* Automatic refresh circuitry
* Selectable row address hold and RAS precharge times
* Facilitates page mode accesses
* Controls 1 MBit DRAMs
* Intelligent burst-mode refresh after page-mode access cycles PRODUCT DESCRIPT
74F1763
117.46 KB
Intelligent dram controller.
INTEGRATED CIRCUITS
74F1763 Intelligent DRAM controller (IDC)
Product specification Supersedes data of 1989 Nov 17 IC15 Data Handbook 1999 Jan 08
Ph.
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