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74HCT138 - 3-to-8 line decoder/demultiplexer

Download the 74HCT138 datasheet PDF. This datasheet also covers the 74HC138 variant, as both devices belong to the same 3-to-8 line decoder/demultiplexer family and are provided as variant models within a single manufacturer datasheet.

Description

The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7).

Features

  • Complies with JEDEC standard no. 7A.
  • Input levels:.
  • For 74HC138: CMOS level.
  • For 74HCT138: TTL level.
  • Demultiplexing capability.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (74HC138-NXP.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

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74HCT138D 3-to-8 line decoder/demultiplexer nexperia

Other Datasheets by NXP Semiconductors

Part Number Description
74HCT132 Quad 2-input NAND Schmitt trigger
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74HCT139-Q100 Dual 2-to-4 line decoder/demultiplexer
74HCT11 Triple 3-input AND gate
74HCT123 Dual retriggerable monostable multivibrator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
74HC138; 74HCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 6 — 28 December 2015 Product data sheet 1. General description The 74HC138; 74HCT138 decodes three binary weighted address inputs (A0, A1 and A2) to eight mutually exclusive outputs (Y0 to Y7). The device features three enable inputs (E1, E2 and E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH. This multiple enable function allows easy parallel expansion to a 1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one inverter. The ‘138’ can be used as an eight output demultiplexer by using one of the active LOW enable inputs as the data input and the remaining enable inputs as strobes. Inputs include clamp diodes.
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