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74LVC573A Octal D-type transparent latch

74LVC573A Description

74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev.5 * 19 February 2013 Product data sheet 1.General.
The 74LVC573A consists of eight D-type transparent latches, featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented.

74LVC573A Features

* 5 V tolerant inputs/outputs, for interfacing with 5 V logic
* Supply voltage range from 1.2 V to 3.6 V
* CMOS low power consumption
* Direct interface with TTL levels
* High-impedance when VCC = 0 V
* Flow-through pinout architecture
* Complies with JEDEC standard:

74LVC573A Applications

* A Latch Enable (LE) input and an Output Enable (OE) input are common to all internal latches. When LE is HIGH, data at the Dn inputs enters the latches. In this condition, the latches are transparent, that is, a latch output changes each time its corresponding D-input changes. When LE is LOW, the l

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Octal D-type transparent latch NXP
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