74VHC126 Datasheet - NXP

74VHC126 Quad buffer/line driver

The 74VHC126; 74VHCT126 are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are speciﬁed in compliance with JEDEC standard No. 7-A. The 74VHC126; 74VHCT126 provide four non-inverting buffer/line drivers with 3-state outputs. The 3-state outputs (nY) a.

74VHC126 Features

* I Balanced propagation delays I All inputs have Schmitt-trigger action I Inputs accept voltages higher than VCC I Input levels: N The 74VHC126 operates with CMOS input level N The 74VHCT126 operates with TTL input level I ESD protection: N HBM JESD22-A114E exceeds 2000 V N MM JESD22-A115-A exceeds 2

74VHC126-NXP.pdf