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BSP206 - P-channel enhancement mode vertical D-MOS transistor

BSP206 Description

DISCRETE SEMICONDUCTORS DATA SHEET BSP206 P-channel enhancement mode vertical D-MOS transistor Product specification File under Discrete Semiconducto.
P-channel enhancement mode vertical D-MOS transistor in a miniature SOT223 envelope and intended for use in relay, high-speed and line-transformer dri.

BSP206 Features

* Very low RDS(on)
* Direct interface to C-MOS, TTL, etc.
* High-speed switching
* No secondary breakdown PINNING - SOT223 1 = gate 2 = drain 3 = source 4 = drain Marking code BSP206 PIN CONFIGURATION QUICK REFERENCE DATA Drain-source voltage Drain current (DC) Drain-

BSP206 Applications

* BSP206 This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications. These products are not designed for use in life support appliances, devi

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P-channel enhancement mode vertical D-MOS transistor NXP
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