HSTL16918 Datasheet - NXP

HSTL16918 HSTL-to-LVTTL memory address latch

The HSTL16918 is a 9-bit to 18-bit D-type latch designed for 3.15 to 3.45 V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels. The HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with it.

HSTL16918 Features

* Inputs meet JEDEC HSTL Std. JESD 8

* 6, and outputs meet Level III specifications PIN CONFIGURATION 2Q1 1Q1 GND D1 D2 VCC D3 1 2 3 4 5 6 7 8 9 48 VCC 47 VCC 46 1Q2 45 2Q2 44 GND 43 1Q3 42 2Q3 41 VCC 40 1Q4 39 2Q4 38 GND 37 1Q5 36 2Q5 35 GND 34 1Q6 33 2Q6 32 VCC 31 1Q7 30 2Q7 29 GND

HSTL16918 Datasheet (92.54 KB)