ADC1004S050 Description
ADC1004S030/040/050 Rev.03 * 7 August 2008 www.DataSheet4U.com Single 10 bits ADC, up to 30 MHz, 40 MHz or 50 MHz Product data sheet 1.Ge.ADC1004S050 Features
* I I I I I I I I I I I I I I 10-bit resolution Sampling rate up to 50 MHz DC sampling allowed One clock cycle conversion only High signal-to-noise ratio over a large analog input frequency range (9.4 effective bits at 4.43 MHz full-scale input at fclk = 40 MHz) No missing codes guaranteed In-Range (IADC1004S050 Applications
* They convert the analog input signal into 10-bit binary-coded digital signals at a maximum sampling rate of 50 MHz. All digital inputs and outputs are Transistor-Transistor Logic (TTL) and CMOS compatible, although a low-level sine wave clock input signal is allowed. The device requires an external
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