NT5CC128M16HP, NT5CB128M16HP Datasheet - Nanya

NT5CC128M16HP 2Gb DDR3 SDRAM H-Die

The 2Gb Double-Data-Rate-3 (DDR3(L)) H-die DRAM is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAMs. The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high speed double-data-rate transfer.

NT5CC128M16HP Features

* and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended DQS or differential DQS pair in a source synchrono

NT5CB128M16HP-Nanya.pdf