NT5CC128M8FN, NT5CB128M8FN Datasheet - Nanya

NT5CC128M8FN 1Gb SDRAM

The 1Gb Double-Data-Rate-3 (DDR3(L)) F-die DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM. The 1Gb chip is organized as 16Mbit x 8 I/Os x 8 banks or 8Mbit x 16 I/Os x 8 bank devices. These synchronous devices achieve high sp.

NT5CC128M8FN Features

* JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM

* Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes

* Power Saving Mode - Partial Array Self Refr

NT5CB128M8FN-Nanya.pdf