CD4044BM Datasheet PDF - National Semiconductor Quad TRI-STATE NOR(NAND) R/S Latches Specs

CD4044BM - Quad TRI-STATE NOR(NAND) R/S Latches

Datasheet Summary

Description

CD4043BM CD4043BC are quad cross-couple TRI-STATE CMOS NOR latches and CD4044BM CD4044BC are quad cross-couple TRI-STATE CMOS NAND latches Each latch has a separate Q output and individual SET and RESET inputs There is a common TRI-STATE ENABLE input for all four latches A logic ‘‘1’’ on the ENABLE

Features

Y Y Y Y Y Y Wide supply voltage range 3V to 15V Low power 100 nW (typ ) High noise immunity 0 45 VDD (typ ) Separate SET and RESET inputs for each latch NOR and NAND configuration TRI-STATE output with common output enable.

Datasheet Details

Part number	CD4044BM
Manufacturer	National Semiconductor
File Size	136.33 KB
Description	Quad TRI-STATE NOR(NAND) R/S Latches
Datasheet	CD4044BM Datasheet
Additional preview pages of the CD4044BM datasheet.

📁 Similar Datasheet

CD4044BM - CMOS QUAD 3-STATE R/S LATCHES (Texas Instruments)

CD4044BMS - CMOS Quad 3 State R/S Latche (Intersil Corporation)

CD4044B - CMOS QUAD 3-STATE R/S LATCHES (RCA)

CD4044B - CMOS QUAD 3-STATE R/S LATCHES (Texas Instruments)

CD4044BC - Quad 3-STATE NAND R/S Latches (Fairchild Semiconductor)

CD4044BE - CMOS QUAD 3-STATE R/S LATCHES (Texas Instruments)

CD4044BF - CMOS QUAD 3-STATE R/S LATCHES (Texas Instruments)

CD4044A - CMOS QUAD 3-STATE R/S LATCHES (RCA)

CD4040A - CMOS 12-Stage Ripple Carry Binary Counters (RCA)

CD4040B - CMOS RIPPLE-CARRY BINARY COUNTER DIVIDERS (RCA)

Full PDF Text Transcription

Click to expand full text

CD4043BM CD4043BC Quad TRI-STATE NOR R S Latches CD4044BM CD4044BC Quad TRI-STATE NAND R S Latches February 1988 CD4043BM CD4043BC Quad TRI-STATE NOR R S Latches CD4044BM CD4044BC Quad TRI-STATE NAND R S Latches General Description CD4043BM CD4043BC are quad cross-couple TRI-STATE CMOS NOR latches and CD4044BM CD4044BC are quad cross-couple TRI-STATE CMOS NAND latches Each latch has a separate Q output and individual SET and RESET inputs There is a common TRI-STATE ENABLE input for all four latches A logic ‘‘1’’ on the ENABLE input connects the latch states to the Q outputs A logic ‘‘0’’ on the ENABLE input disconnects the latch states from the Q outputs resulting in an open circuit condition on the Q output The TRI-STATE feature allows common bussing of the outputs Features Y Y Y Y Y Y

Published: Mar 23, 2005 |